PoC.cache.replacement_policy¶
Supported policies:
Abbr. | Policies | supported |
---|---|---|
RR | round robin | not yet |
RAND | random | not yet |
CLOCK | clock algorithm | not yet |
LRU | least recently used | YES |
LFU | least frequently used | not yet |
Command thruth table:
TagAccess | ReadWrite | Invalidate | Replace | Command |
---|---|---|---|---|
0 | 0 | None | ||
1 | 0 | 0 | 0 | TagHit and reading a cache line |
1 | 1 | 0 | 0 | TagHit and writing a cache line |
1 | 0 | 1 | 0 | TagHit and invalidate a cache line (while reading) |
1 | 1 | 1 | 0 | TagHit and invalidate a cache line (while writing) |
0 | 0 | 1 | Replace cache line |
In a set-associative cache, each cache-set has its own instance of this component.
The input HitWay
specifies the accessed way in a fully-associative or
set-associative cache.
The output ReplaceWay
identifies the way which will be replaced as next by
a replace command. In a set-associative cache, this is the way in a specific
cache set (see above).
Entity Declaration:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 | entity cache_replacement_policy is
generic (
REPLACEMENT_POLICY : string := "LRU";
CACHE_WAYS : positive := 32
);
port (
Clock : in std_logic;
Reset : in std_logic;
-- replacement interface
Replace : in std_logic;
ReplaceWay : out std_logic_vector(log2ceilnz(CACHE_WAYS) - 1 downto 0);
-- cacheline usage update interface
TagAccess : in std_logic;
ReadWrite : in std_logic;
Invalidate : in std_logic;
HitWay : in std_logic_vector(log2ceilnz(CACHE_WAYS) - 1 downto 0)
);
end entity;
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