PoC.io.PulseWidthModulation

GitHub Links

This module generates a pulse width modulated signal, that can be configured in frequency (PWM_FREQ) and modulation granularity (PWM_RESOLUTION).

Entity Declaration:

 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
entity io_PulseWidthModulation is
  generic (
    CLOCK_FREQ                : FREQ                  := 100 MHz;
    PWM_FREQ                  : FREQ                  := 1 kHz;
    PWM_RESOLUTION            : positive              := 8
  );
  port (
    Clock       : in  std_logic;
    Reset       : in  std_logic;
    PWMIn       : in  std_logic_vector(PWM_RESOLUTION - 1 downto 0);
    PWMOut      : out std_logic
  );
end entity;