PoC.mem.ddr3.mem2mig_adapter_Series7

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Adapter between the PoC.Mem interface and the application interface (“app”) of the Xilinx MIG IP core for 7-Series FPGAs.

Simplifies the application interface (“app”) of the Xilinx MIG IP core. The PoC.Mem interface provides single-cycle fully pipelined read/write access to the memory. All accesses are word-aligned. Always all bytes of a word are written to the memory. More details can be found here.

Generic parameters:

  • D_BITS: Data bus width of the PoC.Mem and “app” interface. Also size of one word in bits.
  • DQ_BITS: Size of data bus between memory controller and external memory (DIMM, SoDIMM).
  • MEM_A_BITS: Address bus width of the PoC.Mem interface.
  • APP_A_BTIS: Address bus width of the “app” interface.

Containts only combinational logic.

Entity Declaration:

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entity ddr3_mem2mig_adapter_Series7 is

  generic (
    D_BITS     : positive;
    DQ_BITS    : positive;
    MEM_A_BITS : positive;
    APP_A_BITS : positive
  );
  
  port (
    -- PoC.Mem interface
    mem_req   : in  std_logic;
    mem_write : in  std_logic;
    mem_addr  : in  unsigned(MEM_A_BITS-1 downto 0);
    mem_wdata : in  std_logic_vector(D_BITS-1 downto 0);
    mem_wmask : in  std_logic_vector(D_BITS/8-1 downto 0) := (others => '0');
    mem_rdy   : out std_logic;
    mem_rstb  : out std_logic;
    mem_rdata : out std_logic_vector(D_BITS-1 downto 0);
    
    -- Xilinx MIG IP Core interface
    init_calib_complete : in  std_logic;
    app_rd_data         : in  std_logic_vector((D_BITS)-1 downto 0);
    app_rd_data_end     : in  std_logic;
    app_rd_data_valid   : in  std_logic;
    app_rdy             : in  std_logic;
    app_wdf_rdy         : in  std_logic;
    app_addr            : out std_logic_vector(APP_A_BITS-1 downto 0);
    app_cmd             : out std_logic_vector(2 downto 0);
    app_en              : out std_logic;
    app_wdf_data        : out std_logic_vector((D_BITS)-1 downto 0);
    app_wdf_end         : out std_logic;
    app_wdf_mask        : out std_logic_vector((D_BITS)/8-1 downto 0);
    app_wdf_wren        : out std_logic
  );
  
end entity ddr3_mem2mig_adapter_Series7;