PoC.mem.sdram.ctrl_de0

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Complete controller for ISSI SDR-SDRAM for Altera DE0 Board.

SDRAM Device: IS42S16400F

Configuration

Parameter Description
CLK_PERIOD Clock period in nano seconds. All SDRAM timings are calculated for the device stated above.
CL CAS latency, choose according to clock frequency.
BL Burst length. Choose BL=1 for single cycle memory transactions as required for the PoC.Mem interface.

Tested with: CLK_PERIOD = 7.5 (133 MHz), CL=2, BL=1.

Operation

Command, address and write data is sampled with clk. Read data is also aligned with clk.

For description on clkout see sdram_ctrl_phy_de0.

Synchronous resets are used.

Entity Declaration:

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entity sdram_ctrl_de0 is

  generic (
    CLK_PERIOD  : real;
    CL          : positive;
    BL          : positive);
    
  port (
    clk        : in    std_logic;
    clkout     : in    std_logic;
    rst        : in    std_logic;
    
    user_cmd_valid   : in  std_logic;
    user_wdata_valid : in  std_logic;
    user_write       : in  std_logic;
    user_addr        : in  std_logic_vector(21 downto 0);
    user_wdata       : in  std_logic_vector(15 downto 0);
    user_got_cmd     : out std_logic;
    user_got_wdata   : out std_logic;
    user_rdata       : out std_logic_vector(15 downto 0);
    user_rstb        : out std_logic;
    
    sd_ck      : out   std_logic;
    sd_cke     : out   std_logic;
    sd_cs      : out   std_logic;
    sd_ras     : out   std_logic;
    sd_cas     : out   std_logic;
    sd_we      : out   std_logic;
    sd_ba      : out   std_logic_vector(1 downto 0);
    sd_a       : out   std_logic_vector(11 downto 0);
    sd_dq      : inout std_logic_vector(15 downto 0));
    
end sdram_ctrl_de0;