Which Tool Chains are supported?¶
The PoC-Library and its Python-based infrastructure currently supports the following free and commercial vendor tool chains:
- Synthesis Tool Chains:- Altera Quartus 
 Tested with Quartus-II ≥ 13.0.
 Tested with Quartus Prime ≥ 15.1.
- Intel Quartus 
 Tested with Quartus Prime ≥ 16.1.
- Lattice Diamond 
 Tested with Diamond ≥ 3.6.
- Xilinx ISE 
 Only ISE 14.7 inclusive Core Generator 14.7 is supported.
- Xilinx PlanAhead 
 Only PlanAhead 14.7 is supported.
- Xilinx Vivado 
 Tested with Vivado ≥ 2015.4.
 Due to a limited VHDL language support compared to ISE 14.7, some PoC IP cores need special work arounds. See the synthesis documention section for Vivado for more details.
 
- Altera Quartus 
- Simulation Tool Chains:- Aldec Active-HDL 
 Tested with Active-HDL (or Student-Edition) ≥ 10.3
 Tested with Active-HDL Lattice Edition ≥ 10.2
- Cocotb with Mentor QuestaSim backend 
 Tested with Mentor QuestaSim 10.4d
- Mentor Graphics ModelSim 
 Tested with ModelSim PE (or Student Edition) ≥ 10.5c
 Tested with ModelSim SE ≥ 10.5c
 Tested with ModelSim Altera Edition 10.3d (or Starter Edition)
- Mentor Graphics QuestaSim/ModelSim 
 Tested with Mentor QuestaSim ≥ 10.4d
- Xilinx ISE Simulator 
 Tested with ISE Simulator (iSim) 14.7.
 The Python infrastructure supports isim, but PoC’s simulation helper packages and testbenches rely on VHDL-2008 features, which are not supported by isim.
- Xilinx Vivado Simulator 
 Tested with Vivado Simulator (xsim) ≥ 2016.3.
 The Python infrastructure supports xsim, but PoC’s simulation helper packages and testbenches rely on VHDL-2008 features, which are not fully supported by xsim, yet.
- GHDL + GTKWave 
 Tested with GHDL ≥ 0.34dev and GTKWave ≥ 3.3.70
 Due to ungoing development and bugfixes, we encourage to use the newest GHDL version.
 
- Aldec Active-HDL