PoC.fifo.ic_assembly

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This module assembles a FIFO stream from data blocks that may arrive slightly out of order. The arriving data is ordered according to their address. The streamed output starts with the data word written to address zero (0) and may proceed all the way to just before the first yet missing data. The association of data with addresses is used on the input side for the sole purpose of reconstructing the correct order of the data. It is assumed to wrap so as to allow an infinite input sequence. Addresses are not actively exposed to the purely stream-based FIFO output.

The implemented functionality enables the reconstruction of streams that are tunnelled across address-based transports that are allowed to reorder the transmission of data blocks. This applies to many DMA implementations.

Entity Declaration:

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entity fifo_ic_assembly is
  generic (
    D_BITS : positive;                  -- Data Width
    A_BITS : positive;                  -- Address Bits
    G_BITS : positive                   -- Generation Guard Bits
  );
  port (
    -- Write Interface
    clk_wr : in std_logic;
    rst_wr : in std_logic;
    
    -- Only write addresses in the range [base, base+2**(A_BITS-G_BITS)) are
    -- acceptable. This is equivalent to the test
    --   tmp(A_BITS-1 downto A_BITS-G_BITS) = 0 where tmp = addr - base.
    -- Writes performed outside the allowable range will assert the failure
    -- indicator, which will stick until the next reset.
    -- No write is to be performed before base turns zero (0) for the first
    -- time.
    base   : out std_logic_vector(A_BITS-1 downto 0);
    failed : out std_logic;
    
    addr : in  std_logic_vector(A_BITS-1 downto 0);
    din  : in  std_logic_vector(D_BITS-1 downto 0);
    put  : in  std_logic;
    
    -- Read Interface
    clk_rd : in std_logic;
    rst_rd : in std_logic;
    
    dout : out std_logic_vector(D_BITS-1 downto 0);
    vld  : out std_logic;
    got  : in  std_logic
  );
end entity fifo_ic_assembly;