PoC.mem.ocram.sdp

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Inferring / instantiating simple dual-port memory, with:

  • dual clock, clock enable,
  • 1 read port plus 1 write port.

Both reading and writing are synchronous to the rising-edge of the clock. Thus, when reading, the memory data will be outputted after the clock edge, i.e, in the following clock cycle.

The generalized behavior across Altera and Xilinx FPGAs since Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:

Mixed-Port Read-During-Write
When reading at the write address, the read value will be unknown which is aka. “don’t care behavior”. This applies to all reads (at the same address) which are issued during the write-cycle time, which starts at the rising-edge of the write clock and (in the worst case) extends until the next rising-edge of the write clock.

For simulation, always our dedicated simulation model PoC.mem.ocram.tdp_sim is used.

Entity Declaration:

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entity ocram_sdp is
  generic (
    A_BITS    : positive;                             -- number of address bits
    D_BITS    : positive;                             -- number of data bits
    FILENAME  : string    := ""                       -- file-name for RAM initialization
  );
  port (
    rclk  : in  std_logic;                            -- read clock
    rce   : in  std_logic;                            -- read clock-enable
    wclk  : in  std_logic;                            -- write clock
    wce   : in  std_logic;                            -- write clock-enable
    we    : in  std_logic;                            -- write enable
    ra    : in  unsigned(A_BITS-1 downto 0);          -- read address
    wa    : in  unsigned(A_BITS-1 downto 0);          -- write address
    d     : in  std_logic_vector(D_BITS-1 downto 0);  -- data in
    q     : out std_logic_vector(D_BITS-1 downto 0)   -- data out
  );
end entity;