PoC.mem.ocram.sdp_wf

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Inferring / instantiating simple dual-port memory, with:

  • single clock, clock enable,
  • 1 read port plus 1 write port.

Command truth table:

ce we Command
0 X No operation
1 0 Read only from memory
1 1 Read from and Write to memory

Both reading and writing are synchronous to the rising-edge of the clock. Thus, when reading, the memory data will be outputted after the clock edge, i.e, in the following clock cycle.

Mixed-Port Read-During-Write
When reading at the write address, the read value will be the new data, aka. “write-first behavior”. Of course, the read is still synchronous, i.e, the latency is still one clock cyle.

Entity Declaration:

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entity ocram_sdp_wf is
  generic (
    A_BITS    : positive;                           -- number of address bits
    D_BITS    : positive;                           -- number of data bits
    FILENAME  : string    := ""                     -- file-name for RAM initialization
  );
  port (
    clk : in  std_logic;                            -- clock
    ce  : in  std_logic;                            -- clock-enable
    we  : in  std_logic;                            -- write enable
    ra  : in  unsigned(A_BITS-1 downto 0);          -- read address
    wa  : in  unsigned(A_BITS-1 downto 0);          -- write address
    d   : in  std_logic_vector(D_BITS-1 downto 0);  -- data in
    q   : out std_logic_vector(D_BITS-1 downto 0)   -- data out
  );
end entity;