PoC.mem.ocrom.dp

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Inferring / instantiating dual-port read-only memory, with:

  • dual clock, clock enable,
  • 2 read ports.

The generalized behavior across Altera and Xilinx FPGAs since Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:

WARNING: The simulated behavior on RT-level is not correct.

TODO: add timing diagram TODO: implement correct behavior for RT-level simulation

Entity Declaration:

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entity ocrom_dp is
  generic (
    A_BITS    : positive;
    D_BITS    : positive;
    FILENAME  : string    := ""
  );
  port (
    clk1 : in std_logic;
    clk2 : in std_logic;
    ce1 : in  std_logic;
    ce2 : in  std_logic;
    a1   : in unsigned(A_BITS-1 downto 0);
    a2   : in unsigned(A_BITS-1 downto 0);
    q1   : out std_logic_vector(D_BITS-1 downto 0);
    q2   : out std_logic_vector(D_BITS-1 downto 0)
  );
end entity;