Base.Project¶

Classes

FileTypes: Undocumented.
Environment: An enumeration.
ToolChain: An enumeration.
Tool: An enumeration.
VHDLVersion: An enumeration.
Project: Undocumented.
FileSet: Undocumented.
VHDLLibrary: Undocumented.
File: Undocumented.
ProjectFile: Undocumented.
ConstraintFile: Undocumented.
SettingsFile: Undocumented.
SourceFile: Undocumented.
VHDLSourceFile: Undocumented.
VerilogSourceFile: Undocumented.
PythonSourceFile: Undocumented.
CocotbSourceFile: Undocumented.

class Base.Project.FileTypes[source]¶

Inheritance

Members

Extension()[source]¶

_FlagsArithmeticMixin__bits¶

_FlagsArithmeticMixin__create_flags_instance(bits)¶

_Flags__internal_str()¶

bits_from_simple_str(s)¶

bits_from_str(s)¶: Converts the output of __str__ into an integer.

data¶

from_simple_str(s)¶: Accepts only the output of to_simple_str(). The output of __str__() is invalid as input.

from_str(s)¶: Accepts both the output of to_simple_str() and __str__().

is_disjoint(*flags_instances)¶

is_member¶: flags.is_member is a shorthand for flags.properties is not None. If this property is False then this Flags instance has either zero bits or holds a combination of flag member bits. If this property is True then the bits of this Flags instance match exactly the bits associated with one of the members. This however doesn’t necessarily mean that this flag instance isn’t a combination of several flags because the bits of a member can be the subset of another member. For example if member0_bits=0x1 and member1_bits=0x3 then the bits of member0 are a subset of the bits of member1. If a flag instance holds the bits of member1 then Flags.is_member returns True and Flags.properties returns the properties of member1 but __len__() returns 2 and __iter__() yields both member0 and member1.

name¶

properties¶

Returns:	Returns None if this flag isn’t an exact member of a flags class but a combination of flags,

returns an object holding the properties (e.g.: name, data, index, ...) of the flag otherwise. We don’t store flag properties directly in Flags instances because this way Flags instances that are the (temporary) result of flags arithmetic don’t have to maintain these fields and it also has some benefits regarding memory usage.

to_simple_str()¶

class Base.Project.Environment[source]¶

An enumeration.

Inheritance

Members

Any = 0¶

Simulation = 1¶

Synthesis = 2¶

class Base.Project.ToolChain[source]¶

An enumeration.

Inheritance

Members

Any = 0¶

Aldec_ActiveHDL = 10¶

Aldec_RivieraPRO = 15¶

Altera_Quartus = 20¶

Altera_ModelSim = 21¶

Cocotb = 30¶

GHDL_GTKWave = 40¶

Intel_Quartus = 50¶

Intel_ModelSim = 51¶

Lattice_Diamond = 60¶

Lattice_Synplify = 65¶

Mentor_ModelSim = 70¶

Mentor_QuestaSim = 75¶

Xilinx_ISE = 80¶

Xilinx_PlanAhead = 81¶

Xilinx_Vivado = 82¶

class Base.Project.Tool(*_)[source]¶

An enumeration.

Inheritance

Members

Any = 0¶

Aldec_aSim = ('ASIM', 'Aldec Active-HDL', 'Aldec Active-HDL')¶

Aldec_rPro = ('RPRO', 'Aldec Riviera-PRO', 'Aldec Riviera-PRO')¶

Altera_Quartus_Map = ('QMAP', 'Quartus Map', 'Altera Quartus Map (quartus_map)')¶

Cocotb_QuestaSim = ('COCO', 'Cocotb', 'Coroutine Cosimulation Testbench (Cocotb)')¶

GHDL = ('GHDL', 'GHDL', 'GHDL')¶

GTKwave = ('GTKW', 'GTKWave', 'GTKWave')¶

Lattice_LSE = ('LSE', 'Lattice LSE', 'Lattice Synthesis Engine (LSE)')¶

Mentor_vSim = ('VSIM', 'Mentor ModelSim', 'Mentor Graphics ModelSim (vSim)')¶

Xilinx_iSim = ('XSIM', 'Xilinx iSim', 'Xilinx ISE Simulator (iSim)')¶

Xilinx_XST = ('XST', 'Xilinx XST', 'Xilinx Synthesis Tool (XST)')¶

Xilinx_CoreGen = ('CG', 'Xilinx CoreGen', 'Xilinx Core Generator Tool (CoreGen)')¶

Xilinx_xSim = ('XSIM', 'Xilinx xSim', 'Xilinx Vivado Simulator (xSim)')¶

Xilinx_Synth = ('VIVADO', 'Xilinx Vivado Synthesis', 'Xilinx Vivado Synthesis (synth)')¶

Xilinx_IPCatalog = ('XCI', 'Xilinx Vivado IP Catalog', 'Xilinx Vivado IP Catalog')¶

class Base.Project.VHDLVersion(*_)[source]¶

An enumeration.

Inheritance

Members

Any = 0¶

VHDL87 = 87¶

VHDL93 = 93¶

VHDL2002 = 2002¶

VHDL2008 = 2008¶

class Base.Project.Project(name)[source]¶

Inheritance

Members

Name¶

RootDirectory¶

Board¶

Device¶

Environment¶

ToolChain¶

Tool¶

VHDLVersion¶

CreateFileSet(name, setDefault=True)[source]¶

AddFileSet(fileSet)[source]¶

FileSets¶

DefaultFileSet¶

AddFile(file, fileSet=None)[source]¶

AddSourceFile(file, fileSet=None)[source]¶

Files(fileType=<FileTypes(Text|ProjectFile|FileListFile|RulesFile|SourceFile|VHDLSourceFile|VerilogSourceFile|PythonSourceFile|CocotbSourceFile|ConstraintFile|UcfConstraintFile|XdcConstraintFile|SdcConstraintFile|LdcConstraintFile|SettingsFile|QuartusSettingsFile) bits=0xFFFF>, fileSet=None)[source]¶

ExtractVHDLLibrariesFromVHDLSourceFiles()[source]¶

VHDLLibraries¶

ExternalVHDLLibraries¶

AddExternalVHDLLibraries(library)[source]¶

GetVariables()[source]¶

pprint(indent=0)[source]¶

class Base.Project.FileSet(name, project=None)[source]¶

Inheritance

Members

Name¶

Project¶

Files¶

AddFile(file)[source]¶

AddSourceFile(file)[source]¶

class Base.Project.VHDLLibrary(name, project=None)[source]¶

Inheritance

Members

Name¶

Project¶

Files¶

AddFile(file)[source]¶

class Base.Project.File(file, project=None, fileSet=None)[source]¶

Inheritance

Members

_FileType = <FileTypes() bits=0x0000>¶

Project¶

FileSet¶

FileType¶

FileName¶

Path¶

Open()[source]¶

ReadFile()[source]¶

_ReadContent()[source]¶

class Base.Project.ProjectFile(file, project=None, fileSet=None)[source]¶

Inheritance

Members

_FileType = <FileTypes.ProjectFile bits=0x0002 data=UNDEFINED>¶

FileName¶

FileSet¶

FileType¶

Open()¶

Path¶

Project¶

ReadFile()¶

_ReadContent()¶

class Base.Project.ConstraintFile(file, project=None, fileSet=None)[source]¶

Inheritance

Members

_FileType = <FileTypes.ConstraintFile bits=0x0200 data=UNDEFINED>¶

FileName¶

FileSet¶

FileType¶

Open()¶

Path¶

Project¶

ReadFile()¶

_ReadContent()¶

class Base.Project.SettingsFile(file, project=None, fileSet=None)[source]¶

Inheritance

Members

_FileType = <FileTypes.SettingsFile bits=0x4000 data=UNDEFINED>¶

FileName¶

FileSet¶

FileType¶

Open()¶

Path¶

Project¶

ReadFile()¶

_ReadContent()¶

class Base.Project.SourceFile(file, project=None, fileSet=None)[source]¶

Inheritance

Members

_FileType = <FileTypes.SourceFile bits=0x0010 data=UNDEFINED>¶

FileName¶

FileSet¶

FileType¶

Open()¶

Path¶

Project¶

ReadFile()¶

_ReadContent()¶

class Base.Project.VHDLSourceFile(file, vhdlLibraryName, project=None, fileSet=None)[source]¶

Inheritance

Members

_FileType = <FileTypes.VHDLSourceFile bits=0x0020 data=UNDEFINED>¶

Parse()[source]¶

File¶

FileName¶

FileSet¶

FileType¶

LibraryName¶

Open()¶

Path¶

Project¶

ReadFile()¶

_ReadContent()¶

class Base.Project.VerilogSourceFile(file, project=None, fileSet=None)[source]¶

Inheritance

Members

File¶

FileName¶

FileSet¶

FileType¶

Open()¶

Path¶

Project¶

ReadFile()¶

_ReadContent()¶

_FileType = <FileTypes.VerilogSourceFile bits=0x0040 data=UNDEFINED>¶

class Base.Project.PythonSourceFile(file, project=None, fileSet=None)[source]¶

Inheritance

Members

FileName¶

FileSet¶

FileType¶

Open()¶

Path¶

Project¶

ReadFile()¶

_ReadContent()¶

_FileType = <FileTypes.PythonSourceFile bits=0x0080 data=UNDEFINED>¶

class Base.Project.CocotbSourceFile(file, project=None, fileSet=None)[source]¶

Inheritance

Members

File¶

FileName¶

FileSet¶

FileType¶

Open()¶

Path¶

Project¶

ReadFile()¶

_ReadContent()¶

_FileType = <FileTypes.CocotbSourceFile bits=0x0100 data=UNDEFINED>¶