Simulator.ActiveHDLSimulator

Classes

  • Simulator: Base class for all Simulator classes.
class Simulator.ActiveHDLSimulator.Simulator(host, dryRun, simulationSteps)[source]

Inheritance

Inheritance diagram of Simulator

Members

TOOL_CHAIN = 10
TOOL = ('ASIM', 'Aldec Active-HDL', 'Aldec Active-HDL')
_PrepareSimulator()[source]

Create the Active-HDL executable factory.

_RunAnalysis(_)[source]
_RunSimulation(testbench)[source]
_RunSimulationWithGUI(testbench)[source]
Directories
DryRun
ENVIRONMENT = 1
Host
Log(entry, condition=True)

Write an entry to the local logger.

LogDebug(*args, condition=True, **kwargs)
LogDryRun(*args, condition=True, **kwargs)
LogError(*args, condition=True, **kwargs)
LogFatal(*args, condition=True, **kwargs)
LogInfo(*args, condition=True, **kwargs)
LogNormal(*args, condition=True, **kwargs)
LogQuiet(*args, condition=True, **kwargs)
LogVerbose(*args, condition=True, **kwargs)
LogWarning(*args, condition=True, **kwargs)
Logger

Return the local logger instance.

PoCProject
PrintOverallSimulationReport()[source]
PrintSimulationReportLine(testObject, indent, nameColumnWidth)[source]
Run(testbench, board, vhdlVersion, vhdlGenerics=None)[source]

Write the Testbench message line, create a PoCProject and add the first *.files file to it.

RunAll(fqnList, *args, **kwargs)[source]

Run a list of testbenches. Expand wildcards to all selected testbenches.

TestSuite
TryRun(testbench, *args, **kwargs)[source]

Try to run a testbench. Skip skipable exceptions by printing the error and its cause.

VHDLVersion
VHDL_VERSION = 2008
_AddFileListFile(fileListFilePath)
_CreatePoCProject(projectName, board)
_GetHDLParameters(configSectionName)

Parse option ‘HDLParameters’ for Verilog Parameters / VHDL Generics.

_GetTimeDeltaSinceLastEvent()
_Prepare()
_PrepareEnvironment()
_PrepareEnvironment_ChangeDirectory()

Change working directory to temporary path ‘temp/<tool>’.

_PrepareEnvironment_CreatingDirectory()
_PrepareEnvironment_PurgeDirectory()[source]
_PrepareSimulationEnvironment()[source]
_RunCoverage(testbench)[source]
_RunElaboration(testbench)[source]
_RunView(testbench)[source]
_TryLog(*args, condition=True, **kwargs)