PoC.arith.prng

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This module implementes a Pseudo-Random Number Generator (PRNG) with configurable bit count (BITS). This module uses an internal list of FPGA optimized polynomials from 3 to 168 bits. The polynomials have at most 5 tap positions, so that long shift registers can be inferred instead of single flip-flops.

The generated number sequence includes the value all-zeros, but not all-ones.

Entity Declaration:

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entity arith_prng is
  generic (
    BITS : positive         := 32;
    SEED : std_logic_vector := "0"
  );
  port (
    clk  : in std_logic;
    rst  : in std_logic;                            -- reset value to initial seed
    got  : in std_logic;                            -- the current value has been got, and a new value should be calculated
    val  : out std_logic_vector(BITS - 1 downto 0)  -- the pseudo-random number
  );
end entity;