PoC.arith.same¶

This circuit may, for instance, be used to detect the first sign change and, thus, the range of a two’s complement number.

These components may be chained by using the output of the predecessor as guard input. This chaining allows to have intermediate results available while still ensuring the use of a fast carry chain on supporting FPGA architectures. When chaining, make sure to overlap both vector slices by one bit position as to avoid an undetected sign change between the slices.

Entity Declaration:

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entity arith_same is
  generic (
    N : positive                             -- Input width
  );
  port (
    g : in  std_logic := '1';               -- Guard Input (!g => !y)
    x : in  std_logic_vector(N-1 downto 0); -- Input Vector
    y : out std_logic                       -- All-same Output
  );
end entity;