PoC.bus.wb.fifo_adapter

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Small FIFOs are included in this module, if larger or asynchronous transmit / receive FIFOs are required, then they must be connected externally.

old comments:
UART BAUD rate generator bclk_r = bit clock is rising bclk_x8_r = bit clock times 8 is rising

Entity Declaration:

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entity wb_fifo_adapter is
  port (
    -- Global Reset / Clock
    clk       : in std_logic;
    rst       : in std_logic;
    -- Wishbone interface
    wb_adr_i  : in  std_logic_vector(1 downto 0);
    wb_cyc_i  : in  std_logic;
    wb_dat_i  : in  std_logic_vector(7 downto 0);
    wb_stb_i  : in  std_logic;
    wb_we_i   : in  std_logic;
    wb_ack_o  : out std_logic;
    wb_dat_o  : out std_logic_vector(31 downto 0);
    wb_err_o  : out std_logic;
    wb_rty_o  : out std_logic;
    -- RX FIFO interface
    RX_put    : in  std_logic;
    RX_din    : in  std_logic_vector(7 downto 0);
    RX_full   : out std_logic;
    -- TX FIFO interface
    TX_got    : in  std_logic;
    TX_valid  : out std_logic;
    TX_dout   : out std_logic_vector(7 downto 0)
  );
end entity;