PoC.bus.wb.uart_wrapper

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Wrapper module for PoC.io.uart.rx and PoC.io.uart.tx to support the Wishbone interface. Synchronized reset is used.

Entity Declaration:

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entity uart_wb is
  generic (
    CLOCK_FREQ    : FREQ;
    BAUDRATE      : BAUD;
    RX_OUT_REGS   : boolean
  );
  port (
    clk       : in  std_logic;
    rst       : in  std_logic;
    
    -- FIFO interface
    
    wb_adr_i  : in  std_logic_vector(1 downto 0);
    wb_cyc_i  : in  std_logic;
    wb_dat_i  : in  std_logic_vector(7 downto 0);
    wb_stb_i  : in  std_logic;
    wb_we_i   : in  std_logic;
    wb_ack_o  : out std_logic;
    wb_dat_o  : out std_logic_vector(31 downto 0);
    wb_err_o  : out std_logic;
    wb_rty_o  : out std_logic;
    
    -- debugging
    overflow  : out std_logic;
    
    -- External Pins
    rxd       : in  std_logic;
    txd       : out std_logic
  );
end entity;