PoC.bus.wb.ocram

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This slave supports Wishbone Registered Feedback bus cycles (aka. burst transfers / advanced synchronous cycle termination). The mode “Incrementing burst cycle” (CTI = 010) with “Linear burst” (BTE = 00) is supported.

If your master does support Wishbone Classis bus cycles only, then connect wb_cti_i = “000” and wb_bte_i = “00”.

Connect the ocram of your choice to the ram_* port signals. (Every RAM with single cyle read latency is supported.)

Configuration:

PIPE_STAGES = 1
The RAM output is directly connected to the bus. Thus, the read access latency (one cycle) is short. But, the RAM’s read timing delay must be respected.
PIPE_STAGES = 2
The RAM output is registered again. Thus, the read access latency is two cycles.

Entity Declaration:

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entity ocram_wb is
  generic (
    A_BITS      : positive;
    D_BITS      : positive;
    PIPE_STAGES : integer range 1 to 2
  );
  port (
    clk      : in  std_logic;
    rst      : in  std_logic;
    -- WishBone interface
    wb_cyc_i : in  std_logic;
    wb_stb_i : in  std_logic;
    wb_cti_i : in  std_logic_vector(2 downto 0);
    wb_bte_i : in  std_logic_vector(1 downto 0);
    wb_we_i  : in  std_logic;
    wb_adr_i : in  std_logic_vector(A_BITS-1 downto 0);
    wb_dat_i : in  std_logic_vector(D_BITS-1 downto 0);
    wb_ack_o : out std_logic;
    wb_dat_o : out std_logic_vector(D_BITS-1 downto 0);
    -- RAM interface
    ram_ce   : out std_logic;
    ram_we   : out std_logic;
    ram_a    : out unsigned(A_BITS-1 downto 0);
    ram_d    : out std_logic_vector(D_BITS-1 downto 0);
    ram_q    : in  std_logic_vector(D_BITS-1 downto 0)
  );
end entity ocram_wb;