PoC.io.ddrio.in¶

Instantiates chip-specific DDR input registers.

Both data DataIn_high/low are synchronously outputted to the on-chip logic with the rising edge of Clock. DataIn_high is the value at the Pad sampled with the same rising edge. DataIn_low is the value sampled with the falling edge directly before this rising edge. Thus sampling starts with the falling edge of the clock as depicted in the following waveform.

After power-up, the output ports DataIn_high and DataIn_low both equal INIT_VALUE.

Pad must be connected to a PAD because FPGAs only have these registers in IOBs.

Entity Declaration:

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entity ddrio_in is
  generic (
    BITS          : positive;
    INIT_VALUE    : bit_vector  := x"FFFFFFFF"
  );
  port (
    Clock         : in    std_logic;
    ClockEnable   : in    std_logic;
    DataIn_high   : out   std_logic_vector(BITS - 1 downto 0);
    DataIn_low    : out   std_logic_vector(BITS - 1 downto 0);
    Pad           : in    std_logic_vector(BITS - 1 downto 0)
    );
end entity;