PoC.io.ddrio.inout¶

Instantiates chip-specific DDR input and output registers.

Both data DataOut_high/low as well as OutputEnable are sampled with the rising_edge(Clock) from the on-chip logic. DataOut_high is brought out with this rising edge. DataOut_low is brought out with the falling edge.

OutputEnable (Tri-State) is high-active. It is automatically inverted if necessary. Output is disabled after power-up.

Both data DataIn_high/low are synchronously outputted to the on-chip logic with the rising edge of Clock. DataIn_high is the value at the Pad sampled with the same rising edge. DataIn_low is the value sampled with the falling edge directly before this rising edge. Thus sampling starts with the falling edge of the clock as depicted in the following waveform.

Pad must be connected to a PAD because FPGAs only have these registers in IOBs.

Entity Declaration:

 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15
16
17
18
19

entity ddrio_inout is
  generic (
    BITS          : positive
  );
  port (
    ClockOut        : in    std_logic;
    ClockOutEnable  : in    std_logic;
    OutputEnable    : in    std_logic;
    DataOut_high    : in    std_logic_vector(BITS - 1 downto 0);
    DataOut_low     : in    std_logic_vector(BITS - 1 downto 0);
    
    ClockIn         : in    std_logic;
    ClockInEnable   : in    std_logic;
    DataIn_high     : out   std_logic_vector(BITS - 1 downto 0);
    DataIn_low      : out   std_logic_vector(BITS - 1 downto 0);
    
    Pad             : inout std_logic_vector(BITS - 1 downto 0)
  );
end entity;