PoC.io.iic.Controller¶
The I2C Controller transmitts words over the I2C bus (SerialClock - SCL, SerialData - SDA) and also receives them. This controller utilizes the I2C BusController to send/receive bits over the I2C bus. This controller is compatible to the System Management Bus (SMBus).
Entity Declaration:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 | entity iic_Controller is
generic (
DEBUG : boolean := FALSE;
CLOCK_FREQ : FREQ := 100 MHz;
IIC_BUSMODE : T_IO_IIC_BUSMODE := IO_IIC_BUSMODE_STANDARDMODE;
IIC_ADDRESS : std_logic_vector := (7 downto 1 => '0') & '-';
ADDRESS_BITS : positive := 7;
DATA_BITS : positive := 8;
ALLOW_MEALY_TRANSITION : boolean := TRUE
);
port (
Clock : in std_logic;
Reset : in std_logic;
-- IICController master interface
Master_Request : in std_logic;
Master_Grant : out std_logic;
Master_Command : in T_IO_IIC_COMMAND;
Master_Status : out T_IO_IIC_STATUS;
Master_Error : out T_IO_IIC_ERROR;
Master_Address : in std_logic_vector(ADDRESS_BITS - 1 downto 0);
Master_WP_Valid : in std_logic;
Master_WP_Data : in std_logic_vector(DATA_BITS - 1 downto 0);
Master_WP_Last : in std_logic;
Master_WP_Ack : out std_logic;
Master_RP_Valid : out std_logic;
Master_RP_Data : out std_logic_vector(DATA_BITS - 1 downto 0);
Master_RP_Last : out std_logic;
Master_RP_Ack : in std_logic;
-- tristate interface
Serial : inout T_IO_IIC_SERIAL
);
end entity;
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