PoC.io.vga.timing

GitHub Links

Configuration:

MODE = 0: VGA mode with 640x480 pixels, 60 Hz, frequency(clk) ~ 25 MHz MODE = 1: HD 720p with 1280x720 pixels, 60 Hz, frequency(clk) = 74,5 MHz MODE = 2: HD 1080p with 1920x1080 pixels, 60 Hz, frequency(clk) = 138,5 MHz

MODE = 2 uses reduced blanking => only suitable for LCDs.

For MODE = 0, CVT can be configured: - CVT = false: Use Safe Mode Timing (SMT).

The legacy fall-back mode supported by CRTs as well as LCDs. HSync: low-active. VSync: low-active. frequency(clk) = 25.175 MHz. (25 MHz works => 31 kHz / 59 Hz)
  • CVT = true: The “new” Coordinated Video Timing (since 2003).
    The CVT supports some new features, such as reduced blanking (for LCDs) or aspect ratio encoding. See the web for more details. Standard CRT-based timing (CVT-GTF) has been implemented for best compatibility: HSync: low-active. VSync: high-active. frequency(clk) = 23.75 MHz. (25 MHz works => 31 kHz / 62 Hz)

Usage:

The frequency of clk must be equal to the pixel clock frequency of the selected video mode, see also above.

When using analog output, the VGA color signals must be blanked, during horizontal and vertical beam return. This could be achieved by combinatorial “anding” the color value with “beam_on” (part of “phy_ctrl”) inside the PHY.

When using digital output (DVI), then “beam_on” is equal to “DE” (Data Enable) of the DVI transmitter.

xvalid and yvalid show if xpos respectivly ypos are in a valid range. beam_on is ‘1’ iff both xvalid and yvalid = ‘1’.

xpos and ypos also show the pixel location during blanking. This might be useful in some applications. But be careful, that the ranges differ between SMT and CVT.

Entity Declaration:

 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15
16
17
entity vga_timing is
  generic (
    MODE        : T_IO_VGA_MODE   := VGA_MODE_VGA;
    CVT         : boolean         := false      -- Coordinated Video Timing
  );
  port (
    clk         : in  std_logic;
    rst         : in  std_logic;
    phy_ctrl    : out T_IO_VGA_PHY_CTRL;
    xvalid      : out std_logic;
    yvalid      : out std_logic;
    line_end    : out std_logic;
    screen_end  : out std_logic;
    xpos        : out unsigned(11 downto 0);
    ypos        : out unsigned(10 downto 0)
  );
end entity;