PoC.xil.DRP_BusSync¶
Todo
No documentation available.
Entity Declaration:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 | entity xil_DRP_BusSync is
port (
In_Clock : in std_logic;
In_Enable : in std_logic; --
In_Address : in T_XIL_DRP_ADDRESS; --
In_ReadWrite : in std_logic; --
In_DataIn : in T_XIL_DRP_DATA; --
In_DataOut : out T_XIL_DRP_DATA; --
In_Ack : out std_logic; --
Out_Clock : in std_logic;
Out_Enable : out std_logic; --
Out_Address : out T_XIL_DRP_ADDRESS; --
Out_ReadWrite : out std_logic; --
Out_DataIn : in T_XIL_DRP_DATA; --
Out_DataOut : out T_XIL_DRP_DATA; --
Out_Ack : in std_logic --
);
end entity;
|