PoC.xil.ICAP

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This module wraps Xilinx “Internal Configuration Access Port” (ICAP) primitives in a generic module.
Supported devices are:

  • Spartan-6
  • Virtex-4, Virtex-5, Virtex-6
  • Series-7 (Artix-7, Kintex-7, Virtex-7, Zynq-7000)

Entity Declaration:

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entity xil_ICAP is
  generic (
    ICAP_WIDTH  : string := "X32";          -- Specifies the input and output data width to be used
                              -- Spartan 6: fixed to 16 bit
                              -- Virtex 4:  X8 or X32
                              -- Rest: X8, X16, X32
    DEVICE_ID : bit_vector := X"1234567";       -- pre-programmed Device ID value for simulation
                              -- supported by Spartan 6, Virtex 6 and above
    SIM_CFG_FILE_NAME : string  := "NONE"     -- Raw Bitstream (RBT) file to be parsed by the simulation model
                              -- supported by Spartan 6, Virtex 6 and above
  );
  port (
    clk     : in std_logic;           -- up to 100 MHz (Virtex-6 and above, Virtex-5??)
    disable   : in std_logic;           -- low active enable -> high active disable
    rd_wr   : in std_logic;           -- 0 - write, 1 - read
    busy    : out std_logic;            -- on Series-7 devices always '0'
    data_in   : in std_logic_vector(31 downto 0); -- on Spartan-6 only 15 downto 0
    data_out  : out std_logic_vector(31 downto 0) -- on Spartan-6 only 15 downto 0
  );
end entity;