PoC.misc.gearbox.up_cc

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This module provides a downscaling gearbox with a common clock (cc) interface. It perfoems a ‘byte’ to ‘word’ collection. The default order is LITTLE_ENDIAN (starting at byte(0)). Input “In_Data” and output “Out_Data” are of the same clock domain “Clock”. Optional input and output registers can be added by enabling (ADD_***PUT_REGISTERS = TRUE).

Entity Declaration:

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entity gearbox_up_cc is
  generic (
    INPUT_BITS            : positive  := 24;
    OUTPUT_BITS           : positive  := 32;
    META_BITS             : natural   := 0;
    ADD_INPUT_REGISTERS   : boolean   := FALSE;
    ADD_OUTPUT_REGISTERS  : boolean   := FALSE
  );
  port (
    Clock       : in  std_logic;
    
    In_Sync     : in  std_logic;
    In_Valid    : in  std_logic;
    In_Data     : in  std_logic_vector(INPUT_BITS - 1 downto 0);
    In_Meta     : in  std_logic_vector(META_BITS - 1 downto 0);
    
    Out_Sync    : out std_logic;
    Out_Valid   : out std_logic;
    Out_Data    : out std_logic_vector(OUTPUT_BITS - 1 downto 0);
    Out_Meta    : out std_logic_vector(META_BITS - 1 downto 0);
    Out_First   : out std_logic;
    Out_Last    : out std_logic
  );
end entity;